The present invention relates to the field of transistor fabrication, and more particularly, to a method of fabricating a self-aligned, gate diffused junction field effect transistor.
In general, a junction field effect transistor (JFET) 10 (See FIG. 5) may be constructed by first forming an n-type semiconductor layer 12 on a semi-insulating substrate 14, as shown in FIG 1. A semi-insulating material may be defined as a semiconducting material having an electrical resistivity in the range of about 10.sup.6 to 10.sup.8 ohm-cm. In FIG. 2, the transistor area shown is formed by etching a mesa into the n-type semi-conducting layer 12. Next, referring to FIG. 3, an insulating layer 16 of silicon nitride or silicon dioxide is deposited on the n-type semi-conducting layer 12 to provide a masking layer. A window 18 then is opened through the insulating layer 16 and a p-type layer 20 is selectively formed in the n-type layer 20, either by diffusion or by ion implantation. The thickness and doping concentration in the p-type layer 20 when formed by diffusion, are for a given dopant, determined by the temperature inside the annealing furnace and the time the substrate is exposed to such temperature. In the ion-implantation process, the thickness and doping concentration in the p-type layers are determined by the ion energy and implant dose.
Still referring to FIG. 3, the insulating layer 16 is further patterned to open source/drain contact windows 22 to the n-type semi-conducting layer 12. As represented in FIG. 4, low resistance metal source/drain contacts 26 are formed by depositing and alloying a eutectic mixture of gold and germanium on source/drain regions 30 of the exposed n-type semi-conducting layer 12. Finally, a gate electrode 34 is formed between the source/drain contacts 26 on the p-type layer 20, as shown in FIG. 5. However, the formation of the metal source/drain contacts 26 requires an additional separate step distinct from the step of forming the p-type layer 20.
The process of forming the p-type layer 20 is critical to the performance of the JFET because the thickness and doping concentration of the p-type layer 20 determines the current flow between the source/drain contacts 26 in response to the level of an electrical voltage applied to the gate electrode 34 for a given voltage between the source/drain contacts. In order to manufacture JFET's having predetermined source to drain current characteristics, the process of creating the p-type layer 20 must be both reproducible and reliable. At the present state in the technology of compound semiconductors, the practice of the ion-implantation and diffusion processes are not fully understood sufficiently to provide the manufacture of JFETS with performance characteristics within reasonable limits between devices, and satisfactory reliability.
Such inconsistencies in the characteristics of JFETS manufactured in accordance with these prior art techniques are in part attributable to the difficulty in aligning the gate electrode 34 with the p-type layer 20 because the steps of forming the p-type layer 20 and gate electrode 34 are unrelated. Therefore, the perimeter of the p-type layer 20 tends to be misaligned with respect to the perimeter of the gate electrode 34 at the surface of the layer 12. Such misalignment causes the gate electrode 34 to have relatively high electrical resistance and capacitance, thereby resulting in a JFET with poor high frequency response, i.e., a slow switching time between conductive and nonconductive states.
Therefore, there is need for a method of manufacturing junction field effect transistors in which the source/drain and p-type region may be formed in a continuous step to reduce the time and costs required to manufacture a JFET. A further need exists for a method for manufacturing a JFET in which the p-type layer and gate electrode, or metal gate are easily aligned.